Developing Applications for an FPGA

A step by step process

The process of programing an FPGA is quite similar to programing an embedded processor. As introduced in Table 1, most steps are the same:

Embedded processor FPGA
Model (optional) Model (optional)
Choice of language Choice of language
Development Development
Compilation Compilation
link Place and Route
Test and Debug Test and Debug
Documentation Documentation
Production Production

Designing, editing, compiling, etc. are all standards steps that engineers are accustomed to follow.

Hardware Description Language

Two popular ways to program FPGAs are schematic drawing and HDLs (Hardware Description language) development. If it is possible to build logic circuits of any complexity simply by arranging and connecting logic gates (schematic drawing), this method is not efficient and time consuming. Nowadays, most engineers use Hardware Description Languages (HDL) to express the logic in some easy to use format that can be converted to an array of gates. VHDL and Verilog are the most widely used Hardware Description Language.

An engineer can use HDLs for many things. However, it's most important use is to unambiguously describe a particular circuit. This includes describing its inputs, outputs, and behavior. If Verilog (and VHDL) are very popular among hardware engineers, it is also unknown by most software and system engineers because of its complexity. Figure 1 introduces an example of Verilog program:

// Design Name : first_counter
// File Name : first_counter.v
// Function : This is a 4 bit up-counter with
// Synchronous active high reset and
// with active high enable signal

module first_counter (
  clock , // Clock input of the design
  reset , // active high, synchronous Reset input
  enable , // Active high enable signal for counter
  counter_out // 4 bit vector output of the counter
); // End of port list

//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [3:0] counter_out ;

//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires   
wire clock ;
wire reset ;
wire enable ;

//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;

//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block Name
  // At every rising edge of clock we check if reset is active
  // If active, we load the counter output with 4'b0000
  if (reset == 1'b1) begin
    counter_out <=  #1  4'b0000;
  // If enable is active, then we increment the counter
  else if (enable == 1'b1) begin
    counter_out <=  #1  counter_out + 1;
end // End of Block COUNTER

endmodule // End of Module counter

Figure 1: A counter in Verilog (from

Cx language

We created Cx in 2012 to get rid of the complexity of traditional HDLs. Today, Cx is an open-source language used by engineers and makers who want to efficiently create systems and applications for FPGAs and ASICs. The language has a C-like syntax, it features a strong bit-accurate static typing, and it allows cycle-accurate behavior to be implicitly expressed with structured code. Cx can be compiled into Verilog using the Synflow IDE. It offers the same Quality of Result and performance as HDLs with the simplicity of the C language. Figure 2 introduces an example of Cx program:

package com.synflow.example;

task adder {
    out u8 count;

    u8 counter;
    void loop() {
      print("Counter: ", counter);

Figure 2: A counter in Cx

Cx is designed to make the creation of applications and systems for FPGA interactive and fun.

Programing the FPGA

Once developed, a program for an FPGA can be compiled, synthesized and loaded using software called synthesizers. The most well known synthesizers are Xilinx Vivado, Altera Quartus Prime, and Lattice Diamond provided respectively by Xilinx, Altera, and Lattice. We will teach you in the coming chapters how to use these software but if you are interested about what is a compilation, a synthesis, linking a program, and everything else, please ask us your questions. Figure 3 shows the process of compiling a program for an FPGA.

FPGA Design Flow. Figure 3: FPGA Design Flow (from

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